A design specification for an integrated circuit (IC) or application-specific integrated circuit (ASIC) may be translated into a register transfer level (RTL) description of the circuit. The RTL description is a high-level representation of the circuit design written in a hardware description language (HDL) to represent the intended circuit behavior. After logical verification of the RTL design, a gate level representation or “netlist” of the circuit is derived or synthesized from the RTL description, and used in design of the physical circuit layout.
Unfortunately, functional errors or inconsistencies in the circuit behavior are sometimes detected only late in the design stage, when the netlist undergoes final processing for production. At this stage, which may be referred to as a “post-freeze” stage, a restart of the final processing flow may lead to critical delays in release of the circuit design for production, and may require time-consuming and costly application of gate level corrections to the netlist during pre-production processing. Such delays due to errors or inconsistencies significantly delay production of the circuit, and thus increase the project's overall cost.